Name
Abstract | ||
|---|---|---|
Temperature cycling environmental stress testing (EST) of circuit packs is a standard test procedure for the precipitation of latent defects in order to minimize early product lifecycle customer returns. EST is an expensive, energy-intensive bottleneck in the manufacturing process, one that is based on empiricisms that may be out of date. This presents great opportunity for optimization and test c... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1002/bltj.20175 | Bell Labs Technical Journal |
Field | DocType | Volume |
Bottleneck,Simulation,Real-time computing,Temperature cycling,Environmental stress,Engineering,Product lifecycle,Cost reduction,Reliability engineering,Piecewise,Manufacturing process,Test procedures | Journal | 11 |
Issue | ISSN | Citations |
3 | 1089-7089 | 2 |
PageRank | References | Authors |
0.44 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toby Joyce | 1 | 2 | 1.12 |
| Edward J. Lisay, Jr. | 2 | 2 | 0.44 |
| David E. Dalton | 3 | 2 | 0.44 |
| Jeff M. Punch | 4 | 12 | 4.77 |
| Michael S. Shellmer | 5 | 2 | 0.44 |
| Shirish N. Kher | 6 | 2 | 0.44 |
| suresh goyal | 7 | 120 | 13.77 |