Name
Abstract | ||
|---|---|---|
This paper presents the Wafer Scale Integration research underway at our university. Specifically, we focus here on theApplications, Architectures, Design, and Test areas. Discussed are the philosophy of such an—admittedly aggressive—effort, the evolving infrastructure for the project, the application-driven architectures developed, and the design and test methodology. The first WSI design is a fully parallel FFT wafer, with application to a high-performance, high-speed CW jamming canceller. Other wafer level designs include an L-U decomposition array, using a newly-developed reciprocal cell, and a multipurpose PE array. The transition from basic tools, such as MAGIC, to commercial tools such as CADENCE, and the importance of a high level description language, VHDL, for modeling and simulation is emphasized. The discipline of reconfiguration, and the associated yield models, incorporating a harvesting factor, are also an integral part of the on-going project. Although, the first wafer will be reconfigured usingLaser linking and Cutting on the in-house laser table, alternative recon-figuration approaches for the other wafer designs are also being considered. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1007/BF00925469 | VLSI Signal Processing |
Keywords | Field | DocType |
Systolic Array,Device Under Test,Linear Feedback Shift Register,Automatic Test Pattern Generation,Wafer Level | Automatic test pattern generation,Wafer,Device under test,Modeling and simulation,Computer science,Parallel computing,VHDL,Seven Basic Tools of Quality,Control reconfiguration,Wafer-scale integration | Journal |
Volume | Issue | Citations |
2 | 4 | 0 |
PageRank | References | Authors |
0.34 | 4 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vijay Jain | 1 | 50 | 13.06 |
| D. L. Landis | 2 | 11 | 2.41 |
| D. C. Keezer | 3 | 19 | 4.43 |
| K. T. Wilson | 4 | 0 | 0.34 |
| D. Whittaker | 5 | 0 | 0.34 |