Name
Abstract | ||
|---|---|---|
Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs).Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations.The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders.For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISMVL.2008.11 | ISMVL |
Keywords | Field | DocType |
arbitrary quaternary function,high-performance multi-processor,high-performance quaternary,input-value conversion,quaternary full adder,quaternary output generation,corresponding binary cmos implementation,output generator,appropriate input-value conversion,single pes,very large scale integration,voltage,adders,logic circuits,sequential circuits,combinational circuits,power dissipation | Logic gate,Sequential logic,Adder,Computer science,Voltage,Electronic engineering,CMOS,Combinational logic,Very-large-scale integration,Binary number | Conference |
Citations | PageRank | References |
4 | 0.50 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hirokatsu Shirahama | 1 | 28 | 5.25 |
| Takahiro Hanyu | 2 | 441 | 78.58 |