Title
Design and implementation of FPGA based high-performance intrusion detection system
Abstract
As network technology presses forward, Gigabit Ethernet has become the actual standard for large network installations. Therefore, it is necessary to research on security analysis mechanism, which is capable to process high traffic volume over the high-speed network. This paper proposes FPGA based high-performance IDS to detect and respond variant attacks on high-speed links. Most of all, It is possible through the pattern matching function and heuristic analysis function that is processed in FPGA Logic. In other words, we focus on the network intrusion detection mechanism applied in high-speed network.
Year
DOI
Venue
2006
10.1007/11760146_106
ISI
Keywords
Field
DocType
heuristic analysis function,large network installation,high-speed network,fpga logic,network intrusion detection mechanism,actual standard,high-speed link,high-performance intrusion detection system,security analysis mechanism,gigabit ethernet,network technology press,security analysis,pattern matching,intrusion detection system
Information system,Heuristic,Computer science,Field-programmable gate array,Ethernet,Security analysis,Gigabit Ethernet,Intrusion detection system,Pattern matching,Embedded system
Conference
Volume
ISSN
ISBN
3975
0302-9743
3-540-34478-0
Citations 
PageRank 
References 
2
0.43
3
Authors
3
Name
Order
Citations
PageRank
Byoung-koo Kim1245.68
Young-jun Heo242.52
Jintae Oh3257.28