Name
Abstract | ||
|---|---|---|
Excessive peak power supply noise (PPSN) causes yield loss problem during test. To reduce PPSN, we proposed a new technique called Capture and Shift Toggle Reduction (CASTR). CASTR performs power reduction during dynamic test compaction so the test length overhead is very small. It also includes pseudo Boolean optimization (PBO) and random-based techniques to improve the results. Experimental results show that we can reduce flip-flop toggles, which is highly correlated with PPSN, by 33.4% during shift mode and 41.2% in capture operation simultaneously for the large ISCAS89 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700701 | 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS |
Keywords | DocType | ISSN |
boolean algebra,automatic test pattern generation | Conference | 1089-3539 |
Citations | PageRank | References |
1 | 0.36 | 1 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsiu-Ting Lin | 1 | 2 | 1.06 |
| jenyang wen | 2 | 2 | 1.05 |
| James Li | 3 | 1 | 0.36 |
| Ming-Tung Chang | 4 | 12 | 2.59 |
| Min-Hsiu Tsai | 5 | 7 | 1.65 |
| Sheng-Chih Huang | 6 | 6 | 1.25 |
| Chili-Mou Tseng | 7 | 1 | 0.36 |