Name
Title | ||
|---|---|---|
An Embedded Hardware-Efficient Architecture For Real-Time Cascade Support Vector Machine Classification |
Abstract | ||
|---|---|---|
Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640x480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5x over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SAMOS.2013.6621115 | 2013 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (IC-SAMOS) |
Keywords | Field | DocType |
Field Programmable Gate Arrays, Support Vector Machines, Cascade Classifier, Real-time and Embedded Systems, Parallel Architecture | Structured support vector machine,Facial recognition system,Computer science,Support vector machine,Field-programmable gate array,Cascade,Virtex,Artificial intelligence,Face detection,Contextual image classification,Computer engineering,Machine learning | Conference |
Citations | PageRank | References |
9 | 0.53 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christos Kyrkou | 1 | 102 | 14.05 |
| Theocharis Theocharides | 2 | 205 | 26.83 |
| Christos Savvas Bouganis | 3 | 400 | 49.04 |