Name
Abstract | ||
|---|---|---|
Modern out-of-order processors require a large number of register file access ports. However, adding more ports can drastically increase the delay, power and area of the register file. This relationship imposes constraints on existing superscalar designs while impeding implementation of faster and wider out-of-order processors. In this paper, we present a novel multi-ported register file using concepts from network coding. We split a true multi-ported register file into two interleaved banks, each having half the read and write ports. A third bank, storing the XOR of the write backs to the other two banks, is added to amplify the read and write bandwidth. When compared to a conventional register file, our 8R4W 128-entry coded CRAM register file reduces leakage power by 48%, area by 29% and delay by 9%. In addition, for SPEC2006 benchmarks, our implementation consumes 40% less register file dynamic energy on average with IPC degradation of 3%. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2155620.2155643 | MICRO |
Keywords | Field | DocType |
register file access port,register file,conventional register file,modern out-of-order processor,true multi-ported register file,novel multi-ported register file,leakage power,implementation consumes,cram register file,wider out-of-order processor,microarchitecture,network coding,out of order | File Control Block,Computer science,Stack register,Real-time computing,Computer hardware,Processor register,Status register,Memory data register,Parallel computing,Register file,Control register,Register renaming,Operating system | Conference |
ISSN | ISBN | Citations |
1072-4451 | 978-1-5090-6605-6 | 2 |
PageRank | References | Authors |
0.39 | 19 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vignyan Reddy Kothinti Naresh | 1 | 6 | 0.82 |
| David J. Palframan | 2 | 68 | 3.90 |
| M. H. Lipasti | 3 | 1303 | 110.38 |