Title
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)
Abstract
This paper proposes a unified and reconfigurable Montgomery multiplier architecture which can operate in both primary GF(p) and binary extension fields GF(2^n). The multiplier provides efficient execution of Montgomery multiplication in either field for different operand lengths. It supports any operand length 'n', 1\le n \le N where the upper value of N is application dependent. The final result is obtained in 'n+2' clock cycles for either field. Propagation delay of the design is investigated and found to be comparable with the existing unified multiplier architectures while providing reconfigurability at the same time. The proposed architecture has high order of flexibility and low hardware complexity with critical path delay independent of operand length. The multiplier can find application in, for example, Elliptic curve cryptographic(ECC) processors.
Year
DOI
Venue
2007
10.1109/VLSID.2007.27
VLSI Design
Keywords
Field
DocType
existing unified multiplier architecture,critical path delay,montgomery multiplication,propagation delay,primary gf,operand length,binary extension field,finite fields gf,reconfigurable architecture,reconfigurable montgomery multiplier architecture,different operand length,proposed architecture,finite field,elliptic curve,galois fields,elliptic curve cryptography,critical path,galois field
Architecture,Finite field,Reconfigurability,Propagation delay,Computer science,Operand,Arithmetic,Multiplier (economics),GF(2),Binary number
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-2762-0
6
PageRank 
References 
Authors
0.55
5
3
Name
Order
Citations
PageRank
M. Sudhakar1141.80
R. V. Kamala2121.39
M. B. Srinivas39615.09