Name
Abstract | ||
|---|---|---|
Shared-memory multiprocessor systems use private (or per processor) caches to enhance system performance by reducing average memory access time. In-cache modification of shared data in such systems leads to a data inconsistency problem referred to as the cache coherence problem. A solution to the cache coherence problem must ensure that any read access to shared data is satisfied with the most recent version of that data item. Both hardware-based and software-assisted solutions have been developed, reported in the literature, and implemented in multiprocessors. This paper surveys the impact of cache coherence on multiprocessor architecture design. First, general hardware approaches to dealing with cache coherence in shared-memory multiprocessors are presented. The approaches presented are interconnection medium-dependent, as follows: bus-based, multistage interconnection network (MIN)-based , and crossbarbased . The possibility of implementing protocols in hypercubes is also discussed. Software solutions to cache coherence are also dealt with. Coherency requirements and correctness of protocols are later described. Finally, a performance analysis summary is included. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1016/S0065-2458(08)60546-X | Advances In Computers |
Keywords | DocType | Volume |
system performance,satisfiability,cache coherence | Journal | 40 |
ISSN | Citations | PageRank |
Advances In Computers | 1 | 0.36 |
References | Authors | |
39 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mazin S. Yousif | 1 | 321 | 20.66 |
| M. J. Thazhuthaveetil | 2 | 9 | 2.23 |
| Chita R. Das | 3 | 1046 | 45.21 |