Paper Info
Title
Optimization of Instruction Fetch for Decision Support Workloads
Abstract
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars.In this paper, we focus on Database applications running Decision Support workloads. We characterize the locality patterns of ia database kernel and find frequently executed paths. Using this information, we propose an algorithm to lay out the basic blocks for improved I-fetch.Our results show a miss reduction of 60-98% for realistic I-cache sizes and a doubling of the number of instructions executed between taken branches. As a consequence, we increase the fetch bandwith provided by an aggressive sequential fetch unit from 5.8 for the original code to 10.6 using our proposed layout. Our software scheme combines well with hardware schemes like a Trace Cache providing up to 12.1 instruction per cycle, suggesting that commercial workloads may be amenable to the aggressive I-fetch of future superscalars.
Year
DOI
Venue
1999
10.1109/ICPP.1999.797409
ICPP
Keywords
Field
DocType
decision support workloads,instruction fetch,trace cache,aggressive sequential,database application,aggressive i-fetch,future superscalars,basic block,commercial workloads,improved i-fetch,future wide-issue aggressive superscalars,hardware,profiling,decision support,bandwidth,parallel processing,cultural differences,accuracy,compiler optimization,read only memory,databases,engines,instructions per cycle,performance
Instructions per cycle,Locality,Computer science,Profiling (computer programming),Parallel computing,Decision support system,Optimizing compiler,Fetch,Software,Bandwidth (signal processing)
Conference
ISSN
ISBN
Citations 
0190-3918
0-7695-0350-0
9
PageRank 
References 
Authors
0.84
16
7
Name
Order
Citations
PageRank
Alex Ramirez193462.01
Josep-Ll. Larriba-Pey2162.38
Carlos Navarro3121.22
Xavi Serrano490.84
Mateo Valero54520355.94
Josep Torrellas63838262.89
Larriba-Pey, J.L.7192.61