Name
Abstract | ||
|---|---|---|
Cache optimizations use code transformations to increase the locality of memory accesses and use prefetching techniques to hide latency. For best performance, hardware prefetching units of processors should be complemented with software prefetch instructions. A cache simulation enhanced with a hardware prefetcher is presented to run code for a 3D multigrid solver. Thus, cache misses not predicted can be handled via insertion of prefetch instructions. Additionally, Interleaved Block Prefetching (IBPF), is presented. Measurements show its potential. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/11558958_111 | PARA |
Keywords | Field | DocType |
software prefetch instruction,hardware prefetcher,cache optimizations,interleaved block prefetching,hardware prefetching,prefetching technique,memory access,best performance,iterative numerical code,prefetch instruction,code transformation,cache simulation | Program optimization,Memory bandwidth,CPU cache,Cache,Computer science,Parallel algorithm,Parallel computing,Cache algorithms,Solver,Instruction prefetch,Computer hardware | Conference |
Volume | ISSN | ISBN |
3732 | 0302-9743 | 3-540-29067-2 |
Citations | PageRank | References |
1 | 0.37 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Josef Weidendorfer | 1 | 115 | 17.98 |
| Carsten Trinitis | 2 | 151 | 29.80 |