Title
Maurer computers for pipelined instruction processing†
Abstract
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new mathematical approach to the modelling of micro-architectures and the verification of their correctness and the anticipated speed-up results.
Year
DOI
Venue
2008
10.1017/S0960129507006548
Mathematical Structures in Computer Science
Keywords
Field
DocType
maurer machine,new mathematical approach,non-pipelined instruction processing,basic thread algebra,maurer computer,anticipated speed-up result,pipelined instruction processing,model micro-architectures,program algebra
Automata theory,Programming language,Computer science,Correctness,Process calculus,Thread algebra
Journal
Volume
Issue
ISSN
18
2
0960-1295
Citations 
PageRank 
References 
11
0.72
22
Authors
2
Name
Order
Citations
PageRank
Jan A. Bergstra11445140.42
Cornelis A. Middelburg248749.21