Name
Title | ||
|---|---|---|
An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions |
Abstract | ||
|---|---|---|
1. ABSTRACT This paper describes the Van& VFl FPGA architecture, an innovative architecture based on 0.251 (drawn) (0.18~ Leff)/4-metal technology. It was designed from scratch for high performance, routability and ease-of-use. It supports system level functions (including wide gating functions, dual-port SRAMs, high speed carry chains, and high speed IO blocks) with a symmetrical structure. Additionally, the architecture of each of the critical elements including: variable-grain logic blocks, variable-length-interconnects, dual-port embedded SRAM blocks, I/O blocks and on-chip PLL functions will be described. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1145/296399.296422 | FPGA |
Keywords | Field | DocType |
segmented high performance fpga,wide-gating function,chip,ram,ease of use | Computer architecture,Architecture,Gating,Computer science,FPGA prototype,Field-programmable gate array,Real-time computing | Conference |
ISBN | Citations | PageRank |
1-58113-088-0 | 3 | 0.40 |
References | Authors | |
3 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Om P. Agrawal | 1 | 6 | 1.53 |
| Herman Chang | 2 | 3 | 0.40 |
| Brad Sharpe-Geisler | 3 | 3 | 0.40 |
| Nick Schmitz | 4 | 3 | 0.40 |
| Bai Nguyen | 5 | 3 | 0.40 |
| Jack Wong | 6 | 3 | 0.40 |
| Giap Tran | 7 | 3 | 0.40 |
| Fabiano Fontana | 8 | 3 | 0.40 |
| Bill Harding | 9 | 3 | 0.40 |