Paper Info
Title
A 0.9-V 12-Bit 40-Msps Pipeline Adc For Wireless Receivers
Abstract
A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between 1-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.
Year
DOI
Venue
2010
10.1587/transfun.E93.A.395
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Keywords
Field
DocType
A/D, ADC, pipeline, pseudodifferential amplifier, I/Q sharing, CMFB, common-mode feedback
Electrical efficiency,Nyquist frequency,12-bit,Real-time computing,Effective number of bits,Theoretical computer science,CMOS,WiMAX,Electrical engineering,Mathematics,Operational amplifier,Amplifier
Journal
Volume
Issue
ISSN
E93A
2
1745-1337
Citations 
PageRank 
References 
0
0.34
5
Authors
2
Name
Order
Citations
PageRank
Tomohiko Ito1164.40
Tetsuro Itakura218733.44