Name
Abstract | ||
|---|---|---|
A 9.95-11.3-Gb/s transceiver in 0.13-mu m CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12" of FR4 is equalized resulting in system JGEN under 4 mUI(RMs) and 35 mUI(PP). Power consumption is 800 mw. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.884344 | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Keywords | DocType | Volume |
clock and data recovery (CDR), delay-locked loop (DLL), frequency-locked loop (FLL), phase-locked loop (PLL), transceiver | Journal | 41 |
Issue | ISSN | Citations |
12 | 0018-9200 | 12 |
PageRank | References | Authors |
1.26 | 4 | 14 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| John G. Kenney | 1 | 13 | 3.16 |
| Declan Dalton | 2 | 44 | 30.23 |
| Eric Evans | 3 | 48 | 6.60 |
| Murat Hayri Eskiyerli | 4 | 12 | 1.26 |
| Barry Hilton | 5 | 12 | 1.60 |
| Dave Hitchcox | 6 | 12 | 1.60 |
| Terence Kwok | 7 | 12 | 1.60 |
| daniel m mulcahy | 8 | 12 | 1.60 |
| Chris McQuilkin | 9 | 12 | 1.26 |
| Viswabharath Reddy | 10 | 12 | 1.60 |
| Siva Selvanayagam | 11 | 12 | 1.60 |
| Paul Shepherd | 12 | 12 | 1.94 |
| Ward S. Titus | 13 | 14 | 2.75 |
| Lawrence DeVito | 14 | 12 | 1.26 |