Title
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme
Abstract
In this paper a fast and accurate upper-bound power consumption estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware implementation as a single alternative, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the latency range for different hardware implementations. The presented estimation tool estimates the power consumption for these two hardware alternatives. The computational cost of the presented estimation tool depends linearly on the design complexity as no simulation processes are performed, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate. Overall power consumption estimations are within 卤4% of the actual power consumed with an average of 1% error. However, Logic Elements (LEs) and clock power estimates are accurate with an average error of 8.25% and 6.25%, respectively.
Year
DOI
Venue
2008
10.1109/ISVLSI.2008.45
ISVLSI
Keywords
Field
DocType
sw partitioning tool,accurate upper-bound power consumption,hardware alternative,different hardware implementation,sw partitioning scheme,hardware implementation,novel fpga-based hw,power consumption,actual power,clock power estimate,fast hardware upper-bound power,overall power consumption estimation,estimation tool,very large scale integration,cyclones,field programmable gate arrays,space exploration,upper bound,estimation,hardware,logic,fpga,resource management
Latency (engineering),Computer science,Upper and lower bounds,Field-programmable gate array,Space exploration,Computer hardware,Design space exploration,Very-large-scale integration,Energy consumption,Power consumption
Conference
Citations 
PageRank 
References 
4
0.40
13
Authors
2
Name
Order
Citations
PageRank
M. B. AbdelHalim1457.21
S. E. D. Habib2141.53