Paper Info
Title
Reconfigurable communications for image processing applications
Abstract
This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computation and communication pattern of two distributed motion estimation algorithms, Full Search Block Matching Algorithm and Multi-Resolution Block Matching Algorithm. Experimental results show that the use of the Multi-Resolution method reduces not only the computation time but also the traffic of messages on the NoC. This leads to a lower power consumption in the NoC during the processing time of each image. The studied examples show the importance of the link between algorithms and their mapping onto a programmable fabric, not only regarding computation, but facing communication as well.
Year
DOI
Venue
2006
10.1109/IPDPS.2006.1639480
IPDPS
Keywords
Field
DocType
image processing application,processing time,full search block matching,programmable fabric,multi-resolution method,computation time,reconfigurable communication,image application,multi-resolution block matching algorithm,communication pattern,programmable communication resource,acceleration,pattern matching,network on a chip,mathematical model,motion estimation,distributed computing,distributed algorithms,network on chip,image processing,block matching algorithm,image resolution
Block-matching algorithm,Computer science,Parallel computing,Image processing,Network on a chip,Distributed algorithm,Motion estimation,Pattern matching,Energy consumption,Distributed computing,Computation
Conference
ISBN
Citations 
PageRank 
1-4244-0054-6
0
0.34
References 
Authors
2
3
Name
Order
Citations
PageRank
André B. Soares100.34
Luigi Carro21393166.42
Altamiro A. Susin3829.08