Name
Title | ||
|---|---|---|
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method |
Abstract | ||
|---|---|---|
Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formalmodels with high readability or to naturally model data-path circuits. On the other hand, in order to use such amodel on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petrinets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/PRDC.2002.1185640 | PRDC |
Keywords | Field | DocType |
level oriented formal model,efficient analysis method,state explosion problem,level-oriented model,formal verification,timed asynchronous cir- cuits,partial order reduction algorithm,unnecessary state generation,asynchronous circuit,level-oriented formal model,time petrinets,model data-path circuit,high readability,large circuit,time petri nets.,asynchronous circuit verification,petri nets,partial order reduction | Asynchronous communication,Petri net,Algorithm design,Computer science,Automaton,Correctness,Real-time computing,Partial order reduction,Asynchronous circuit,Distributed computing,Formal verification | Conference |
ISBN | Citations | PageRank |
0-7695-1852-4 | 0 | 0.34 |
References | Authors | |
10 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomoya Kitai | 1 | 12 | 1.73 |
| Yusuke Oguro | 2 | 0 | 0.34 |
| Tomohiro Yoneda | 3 | 353 | 41.62 |
| Eric Mercer | 4 | 0 | 0.34 |
| Chris Myers | 5 | 72 | 10.44 |