Abstract | ||
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Scalable shared memory multiprocessors are promising architectures to achieve teraflops computational power. As they contain a large number of processor and memory elements, such machines have a high probability of failure. In this paper, we investigate an approach based on backward error recovery to provide a highly available scalable shared memory architecture tolerating transient and permanent processor and memory failures. |
Year | DOI | Venue |
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1993 | 10.1007/BFb0020021 | Revised Papers from a Workshop on Hardware and Software Architectures for Fault Tolerance |
Keywords | DocType | ISBN |
scalable shared memory multiprocessors,memory multiprocessors | Conference | 3-540-57767-X |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Michel Banâtre | 1 | 305 | 63.45 |
Alain Gefflaut | 2 | 176 | 24.33 |
Christine Morin | 3 | 226 | 26.78 |