Name
Abstract | ||
|---|---|---|
In this paper, we present an in-depth analysis of transient behavior, mainly glitches, in the parallel encoding and decoding circuits of error correcting codes. First, we found that the probability of a given number of glitches that may accumulate in the encoding/decoding circuit exhibits a Gaussianlike distribution. An estimation methodology was developed so the transient behavior of an ECC for very long word length can be predicted. We confirm that the principle of minimum-equal-weight construction of H-matrix is the best design strategy. Two potential solutions are proposed and examined to reduce the accumulation of glitches. Finally, we present the calculation methods and provide examples of odd-weight-column SEC-DED codes for up to 1024 information bits. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DFTVS.2005.67 | DFT |
Keywords | Field | DocType |
estimation methodology,error correcting codes,transient behavior,calculation method,information bit,decoding circuit,parallel encoding,gaussianlike distribution,decoding circuits,in-depth analysis,best design strategy,long word length,encoding,error correction code,gaussian distribution,logic circuits,decoding | Glitch,Concatenated error correction code,Logic gate,Sequential decoding,Computer science,Algorithm,Electronic engineering,Decoding methods,List decoding,Electronic circuit,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2464-8 | 1 |
PageRank | References | Authors |
0.41 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jien-Chung Lo | 1 | 189 | 28.32 |
| Yu-Lun Wan | 2 | 1 | 0.41 |
| Eiji Fujiwara | 3 | 180 | 31.14 |