Title
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link
Abstract
This paper introduces coded differential (CD) signaling for high-speed parallel electrical links. CD preserves the desirable properties of differential signaling while offering ISI mitigation that is superior to 1-tap decision feedback equalization (DFE) [1-2] at no loss in pin efficiency or throughput. Specifically, CD encodes two bits of data over four binary wires in such a way that post-cursor inter-symbol interference (ISI) is completely eliminated across the entire unit-interval (UI). CD signaling is NRZ on individual wires and is balanced across the bus, meaning over any UI half the four-wire set have a high signaling level while the other half have a low level. The balanced nature of signaling leads to low supply switching noise. Received data is detected differentially by discriminating the difference between the signals on wire pairs without the need for a fixed reference voltage.
Year
DOI
Venue
2012
10.1109/ISSCC.2012.6176953
J. Solid-State Circuits
Keywords
Field
DocType
cd signaling,ui,coded differential bidirectional parallel electrical link,four-wire set,isi mitigation,coded differential signaling,unit-interval,1-tap decision feedback equalization,post-cursor intersymbol interference,bit rate 16 gbit/s,low supply switching noise,high-speed parallel electrical links,interference suppression,nrz,decision feedback equalisers,intersymbol interference,multiplexing,decoding,prototypes
Differential signaling,Intersymbol interference,Timing margin,Computer science,Communication channel,Electronic engineering,Encoder,Throughput,Decoding methods,Encoding (memory)
Conference
Volume
Issue
ISSN
47
12
0193-6530
ISBN
Citations 
PageRank 
978-1-4673-0376-7
6
0.82
References 
Authors
4
9
Name
Order
Citations
PageRank
Amir Amirkhany16312.75
Kambiz Kaviani2488.77
Aliazam Abbasfar317325.09
H. Md. Shuaeb Fazeel4243.79
Wendemagegnehu T. Beyene5377.29
Chikara Hoshino6102.57
Chris J. Madden7709.71
Ken Chang8143.25
Chuck Yuan9184.67