Name
Title | ||
|---|---|---|
Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking |
Abstract | ||
|---|---|---|
In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1016/j.tcs.2008.03.032 | Theor. Comput. Sci. |
Keywords | DocType | Volume |
VHDL behavioral description,Semi-formal verification,mixed-signal circuit,steady state behavior,SAT-based property checking,Property checking,verification method,discrete model,industrial design flow,proposed verification methodology,formal digital verification,formal verification method,industrial mixed-signal circuit,Mixed-signal,verification methodology,Formal verification | Journal | 404 |
Issue | ISSN | Citations |
3 | Theoretical Computer Science | 0 |
PageRank | References | Authors |
0.34 | 18 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jens Schönherr | 1 | 8 | 5.40 |
| Martin Freibothe | 2 | 5 | 2.27 |
| Bernd Straube | 3 | 195 | 37.41 |
| Jörg Bormann | 4 | 45 | 9.95 |