Name
Abstract | ||
|---|---|---|
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange for a more complex design of the routers. Another, possibly alternative, approach is to build multiple parallel physical networks (multi-planes) with smaller channels and simpler router organizations. We present a comparative analysis of these two approaches based on analytical models and on a comprehensive set of experimental results including both synthesized hardware implementations and system-level simulations. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1837274.1837315 | DAC |
Keywords | Field | DocType |
complex design,virtual channel,multi-core architecture,efficient communication infrastructure,physical channel,comparative analysis,analytical model,channel slicing,comprehensive set,multiple parallel physical network,packet-switched networks-on-chip,multiple physical network,network-on-chip,space exploration,nickel,system on a chip,integrated circuit design,network on chip,computer architecture,bandwidth,network topology,throughput,network on a chip,network routing | System on a chip,Computer science,Deadlock,Communication channel,Network on a chip,Real-time computing,Bandwidth (signal processing),Router,Throughput,Virtual channel | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-4244-6677-1 | 36 |
PageRank | References | Authors |
1.65 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young Jin Yoon | 1 | 36 | 1.65 |
| Nicola Concer | 2 | 164 | 8.90 |
| Michele Petracca | 3 | 239 | 16.21 |
| Luca Carloni | 4 | 53 | 3.91 |