Paper Info
Title
Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach
Abstract
We present a high qualitative reconfigurability method forfault-tolerant memory systems against radiation influence onsemiconductors. Its novelty lies in a joint failure repairmechanism. It uses a concurrent on-line technique based on asynchronous built-in current sensors (BICS), parity check and cold spare modules against electrical abnormal behaviour due tolatch-up (LU), and the Hamming SEC code to counterattack singleerror upset (SEU), manifested in logical failures. Completereliability computations, which underlie the proposed scheme, searchfor a 99.902% tolerance, thought to meet typical spatial irradiationconditions, to the cost of a small hardware overhead (2 spare(additional) 1K1 modules for each 1K16 of a memory system of 512K16,and Mean Time To Failure = 10−7 h−1). Finally, as weenvisage a 2.4 μm CMOS implementation, we performed complexityestimations, which show that the supplementary self-toleranceensuring circuitry involves an overhead of 0.0094% for a 512K16memory. The recovering latency is minimised. For SEU in DRAM itrequires zero latency and no more than the duration of an equivalentrefresh cycle in SRAM. LU reflects a locality property, as only theaffected module is submitted to the recovering algorithm.
Year
DOI
Venue
1999
10.1023/A:1008378128757
J. Electronic Testing
Keywords
Field
DocType
built-in current sensor,hamming SEC code,latch-up,memory system,single event upset
Hamming code,Registered memory,Interleaved memory,Computer science,Static random-access memory,Real-time computing,Electronic engineering,Fault tolerance,Single event upset,Memory architecture,Embedded system,Memory refresh
Journal
Volume
Issue
ISSN
14
1-2
1573-0727
Citations 
PageRank 
References 
0
0.34
9
Authors
2
Name
Order
Citations
PageRank
Octavian-Dumitru Mocanu100.34
Joan Oliver221.72