A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process - Citegraph

Paper Info

Title
A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

Abstract
This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel stri...

Year	DOI	Venue
2005	10.1109/JSSC.2005.845995	IEEE Journal of Solid-State Circuits
Keywords	DocType	Volume
Random access memory,CMOS process,Read-write memory,Capacitance,Large scale integration,Standards development,Costs,CMOS technology,Decoding,Semiconductor device noise	Journal	40
Issue	ISSN	Citations
5	0018-9200	0
PageRank	References	Authors
0.34	2	15

Authors (15 rows)

Cited by (0 rows)

References (2 rows)

Name	Order	Citations	PageRank
M. Shirahama	1	0	0.34
Y. Agata	2	0	0.34
T. Kawasaki	3	0	0.34
R. Nishihara	4	0	0.34
W. Abe	5	1	0.82
N. Kuroda	6	6	3.46
H. Sadakata	7	0	0.34
T. Uchikoba	8	1	0.82
Takahashi , K. *	9	32	17.54
K. Egashira	10	0	0.34
S. Honda	11	0	0.34
Miho Miura	12	0	0.34
S. Hashimoto	13	0	0.34
H. Kikukawa	14	3	1.95
Hiroyuki Yamauchi	15	180	30.79

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