Name
Abstract | ||
|---|---|---|
This paper presents a semi-systolic architecture for decoding cyclic linear error-correcting codes at high speed. The architecture implements a variant of Tanner's Algorithm B, modified for simpler and faster implementation. The main features of the architecture are low computational complexity, a simple, regular arrangement of cells for easy layout, short critical paths, and a high clock rate. A prototype chip has been designed to decode a 73-bit perfect difference set code. This 4600μ m ×6800μ m chip should achieve 25MHz decoding in 2μ m n -well cMOS. The success of the implementation illustrates the value of using technology dependent constraints and cost measures to guide the design of algorithms and architectures. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1016/0166-218X(91)90111-9 | Discrete Applied Mathematics |
Keywords | Field | DocType |
codecs,semi-systolic decoder,threshold decoding,decoding algorithm,pdssc-73 error-correcting code,correction,decoder for error correction,systolic architecture,perfect difference set code,error correction,tanner's algorithm,error correction code | Concatenated error correction code,Constant-weight code,Computer science,Parallel computing,Error detection and correction,Chip,Soft-decision decoder,Decoding methods,Clock rate,Computational complexity theory | Journal |
Volume | Issue | ISSN |
33 | 1-3 | Discrete Applied Mathematics |
Citations | PageRank | References |
5 | 2.32 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K Karplus | 1 | 952 | 279.66 |
| Habib Krit | 2 | 5 | 2.32 |