Name
Abstract | ||
|---|---|---|
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates the generation of IP core interfaces allowing these to be used as C functions transparently from within C source codes using a reconfigurable computing compiler. We also show how this same tool can be used to support run-time reconfiguration on FPGAs by generating a common wrapper that interfaces to multiple cores |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/FPL.2006.311254 | FPL |
Keywords | Field | DocType |
c source codes,c language,reconfigurable architectures,reconfigurable computing compiler,industrial property,ip core interface generation,field programmable gate arrays,program compilers,reconfigurable computing,source code | Source code,Computer science,FpgaC,Automation,Real-time computing,Industrial property,Control reconfiguration,Computer architecture,Parallel computing,Field-programmable gate array,Compiler,Embedded system,Reconfigurable computing | Conference |
ISSN | ISBN | Citations |
1946-1488 | 1-4244-0312-X | 6 |
PageRank | References | Authors |
0.67 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhi Guo | 1 | 191 | 15.14 |
| Abhishek Mitra | 2 | 142 | 10.24 |
| Najjar, Walid A. | 3 | 2011 | 183.19 |