Paper Info
Title
Performance study of a compiler/hardware approach to embedded systems security
Abstract
Trusted software execution, prevention of code and data tampering, authentication, and providing a secure environment for software are some of the most important security challenges in the design of embedded systems. This short paper evaluates the performance of a hardware/software co-design methodology for embedded software protection. Secure software is created using a secure compiler that inserts hidden codes into the executable code which are then validated dynamically during execution by a reconfigurable hardware component constructed from Field Programmable Gate Array (FPGA) technology. While the overall approach has been described in other papers, this paper focuses on security-performance tradeoffs and the effect of using compiler optimizations in such an approach. Our results show that the approach provides software protection with modest performance penalty and hardware overhead.
Year
DOI
Venue
2005
10.1007/11427995_56
ISI
Keywords
Field
DocType
hardware overhead,secure environment,hardware approach,software co-design methodology,overall approach,performance study,reconfigurable hardware component,secure software,embedded software protection,trusted software execution,software protection,embedded systems security,secure compiler,embedded software,field programmable gate array,embedded system,compiler optimization,reconfigurable hardware
Computer security,Computer science,Software security assurance,Optimizing compiler,Software,Computer hardware,Software visualization,Software development,Embedded software,Compiler,Software construction,Operating system,Embedded system
Conference
Volume
ISSN
ISBN
3495
0302-9743
3-540-25999-6
Citations 
PageRank 
References 
2
0.41
5
Authors
6
Name
Order
Citations
PageRank
Kripashankar Mohan120.41
Bhagirath Narahari233142.59
Rahul Simha3325.16
Paul Ott4211.35
Alok N. Choudhary524222.44
Joseph Zambreno637744.73