Name
Title | ||
|---|---|---|
Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks |
Abstract | ||
|---|---|---|
This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a)techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISMVL.2011.21 | ISMVL |
Keywords | Field | DocType |
fault tolerant computing paradigm,expected nano-centric processing hardware,hundred iteration,robust fault-tolerant computing,five-input single-output network,fault tolerant property,fault tolerant logic network,hop field gate,hopfield gates,random molecular phenomena,correct output,logic networks,logic design,hopfield network,fault tolerant,logic gates,network design,molecular electronics,noise,fault tolerance,merging | Stuck-at fault,Logic synthesis,Digital electronics,Logic gate,Sequential logic,Computer science,Logic optimization,Electronic engineering,Logic family,Computer engineering,Hopfield network | Conference |
ISSN | Citations | PageRank |
0195-623X | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. H. Tran | 1 | 0 | 0.34 |
| S. N. Yanushkevich | 2 | 12 | 3.70 |
| S. E. Lyshevski | 3 | 5 | 1.88 |
| V. P. Shmerko | 4 | 10 | 3.17 |