Name
Abstract | ||
|---|---|---|
This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/92.386220 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
design process,system testing,process design,computer bugs,computer architecture,vlsi,logic,natural languages,silicon | Programming language,System testing,Computer science,Software bug,Electronic engineering,Process design,Natural language,Engineering design process,Symbolic execution,Very-large-scale integration,Debugging | Journal |
Volume | Issue | ISSN |
3 | 2 | 1063-8210 |
Citations | PageRank | References |
44 | 5.27 | 7 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ashok K. Chandra | 1 | 3116 | 1215.02 |
| Vijay S. Iyengar | 2 | 897 | 111.16 |
| D. Jameson | 3 | 44 | 5.27 |
| R. V. Jawalekar | 4 | 51 | 9.52 |
| Indira Nair | 5 | 143 | 23.45 |
| Barry K. Rosen | 6 | 2021 | 327.61 |
| Michael P. Mullen | 7 | 44 | 5.27 |
| J. Yoon | 8 | 44 | 5.27 |
| Roy Armoni | 9 | 63 | 6.63 |
| Daniel Geist | 10 | 512 | 50.51 |
| Yaron Wolfsthal | 11 | 419 | 39.79 |