Abstract | ||
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This paper describes an implementation of a conservative parallel distributed simulator that has been used to simulate a high fidelity model of ATM networks. Important optimisations of the simulator for this application are described. The performance of the simulator is reported on up to 12 processors and compared with a sequential implementation. It is seen that the simulator gives good speedup and better performance than the sequential implementation. It is noted that the low overhead of the simulator relies on there being good lookahead in realistic models of ATM networks. Some situations where this lookahead is significantly reduced are described together with future extensions to fix these problems. |
Year | DOI | Venue |
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1997 | 10.1145/268826.268913 | Proceedings of the eleventh workshop on Parallel and distributed simulation |
Keywords | Field | DocType |
processors,design optimization,speedup,tcpip,parallel processing,switches,asynchronous transfer mode,discrete event simulation,computational modeling,computer science,complex networks | High fidelity,Computer architecture simulator,Computer science,Real-time computing,Asynchronous Transfer Mode,Complex network,Atmosphere (unit),Speedup,Distributed computing,Simulation,Parallel computing,Internet protocol suite,Discrete event simulation | Conference |
Volume | Issue | ISSN |
27 | 1 | 0163-6103 |
ISBN | Citations | PageRank |
0-8186-7965-4 | 3 | 0.49 |
References | Authors | |
5 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
John G. Cleary | 1 | 1791 | 365.78 |
Jya-Jang Tsai | 2 | 71 | 12.33 |