Paper Info
Title
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
Abstract
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results
Year
DOI
Venue
2006
10.1109/TCAD.2006.881332
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
Field
DocType
complementary approach,digital integrated circuit,Digital Integrated Circuits,statistical timing analysis,different process variation condition,EinsTimer static timing analyzer,circuit performance,statistical temperature,timing analysis result,Parametric Yield Prediction,Vdd variation,Statistical Timing,bounded timing methodology
Linear combination,Algorithm design,Computer science,Electronic engineering,Application-specific integrated circuit,Real-time computing,Chip,Integrated circuit design,Parametric statistics,Static timing analysis,Probabilistic logic
Journal
Volume
Issue
ISSN
25
11
0278-0070
ISBN
Citations 
PageRank 
1-58113-688-9
78
15.32
References 
Authors
15
5
Name
Order
Citations
PageRank
J. A.G. Jess111118.51
K. Kalafala28115.78
Srinath R. Naidu37815.32
Ralph H. J. M Otten4417130.84
C. Visweswariah550758.12