Name
Abstract | ||
|---|---|---|
Traditional dynamic scheduler designs use one issue queue entry per instruction, regardless of the actual number of operands actively involved in the wakeup process. We propose Instruction Packing---a novel microarchitectural technique that reduces both delay and power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with, at most, one nonready register source operand at the time of dispatch. Our results show that this technique results in 40% reduction of the IQ power and 14% reduction in scheduling delay with negligible IPC degradations. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1138035.1138037 | TACO |
Keywords | Field | DocType |
energy-efficient instruction scheduling,low power,novel microarchitectural technique,actual number,technique result,issue queue entry,issue queue,additional key words and phrases: issue queue,power consumption,negligible ipc degradation,instruction packing,iq power,associative part,out of order,instruction scheduling,energy efficient,dynamic scheduling | Multilevel queue,Instruction register,Instruction scheduling,Computer science,Multilevel feedback queue,Scheduling (computing),Queue,Operand,Parallel computing,Real-time computing,Earliest deadline first scheduling | Journal |
Volume | Issue | Citations |
3 | 2 | 5 |
PageRank | References | Authors |
0.44 | 32 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joseph J. Sharkey | 1 | 124 | 8.44 |
| Dmitry Ponomarev | 2 | 893 | 56.45 |
| Kanad Ghose | 3 | 1220 | 113.50 |
| Oguz Ergin | 4 | 424 | 25.84 |