Name
Abstract | ||
|---|---|---|
Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/SOCC.2011.6085127 | SoCC |
Keywords | Field | DocType |
switched capacitor networks,optimisation,switched-capacitor analog integrated circuits,integrated circuit interconnections,circuit layout,analogue integrated circuits,wire interconnection,layout generator,physical realization,paralleling square unit capacitors,capacitor ratio,yield-award,layout modification,yield-award placement optimization,spatial correlation,random variation | Integrated circuit layout,Capacitor,Computer science,Switched capacitor,Electronic engineering,Decoupling capacitor,Electronic circuit,Interconnection,Electrical engineering,Integrated circuit | Conference |
ISSN | ISBN | Citations |
2164-1676 E-ISBN : 978-1-4577-1615-7 | 978-1-4577-1615-7 | 1 |
PageRank | References | Authors |
0.37 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chien-Chih Huang | 1 | 224 | 10.26 |
| Jwu-E Chen | 2 | 223 | 28.37 |
| Pei-Wen Luo | 3 | 74 | 8.22 |
| Chin-Long Wey | 4 | 316 | 56.51 |