Name
Title | ||
|---|---|---|
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. |
Abstract | ||
|---|---|---|
This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2013.2284647 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Integrated circuit modeling,Arrays,Hardware,Delays,Reliability engineering | Multi-chip module,Computer science,Microprocessor,Circuit design,Electronic engineering,Chip,Integrated circuit design,eDRAM,Physical design,Computer hardware,Multi-core processor,Embedded system | Journal |
Volume | Issue | ISSN |
49 | 1 | 0018-9200 |
Citations | PageRank | References |
8 | 1.28 | 5 |
Authors | ||
25 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| James D. Warnock | 1 | 54 | 6.47 |
| Yuen H. Chan | 2 | 138 | 29.22 |
| Hubert Harrer | 3 | 17 | 4.72 |
| Sean M. Carey | 4 | 76 | 15.11 |
| Gerard Salem | 5 | 64 | 6.71 |
| Doug Malone | 6 | 31 | 4.17 |
| Ruchir Puri | 7 | 515 | 71.90 |
| Jeffrey A. Zitz | 8 | 18 | 2.74 |
| Adam Jatkowski | 9 | 10 | 2.34 |
| Gerald Strevig | 10 | 16 | 2.34 |
| Ayan Datta | 11 | 14 | 3.14 |
| Anne E. Gattiker | 12 | 117 | 17.78 |
| Aditya Bansal | 13 | 116 | 17.19 |
| G. Mayer | 14 | 40 | 5.26 |
| Yiu-Hing Chan | 15 | 33 | 4.76 |
| Mark D. Mayo | 16 | 62 | 10.30 |
| David L. Rude | 17 | 28 | 3.33 |
| Leon J. Sigal | 18 | 39 | 6.61 |
| Thomas Strach | 19 | 37 | 6.57 |
| Howard H. Smith | 20 | 28 | 3.33 |
| Huajun Wen | 21 | 34 | 3.96 |
| Pak-kin Mak | 22 | 64 | 13.35 |
| Chung-Lung Kevin Shum | 23 | 8 | 1.28 |
| Donald W. Plass | 24 | 190 | 33.42 |
| Charles F. Webb | 25 | 24 | 2.81 |