Paper Info
Title
Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency
Abstract
A high-speed phase-adjustable read-only-memory less direct digital frequency synthesizer employing trigonometric quadruple angle formula is presented. A ten-stage pipelining architecture is employed based upon decomposition of phase operands. Spectral purity is better than -130 dBc for the worst case spurious-free dynamic range. The resolution is up to 12 bits. Most importantly, the output sinusoidal frequency is higher than 40 MHz, which is far higher than the 32-MHz requirement of Korean personal communications system, global system for mobile communications, and Bluetooth. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is limited and the resolution is preserved
Year
DOI
Venue
2006
10.1109/TCSII.2006.882236
IEEE Trans. on Circuits and Systems
Keywords
DocType
Volume
phase-adjustable pipelining rom-less direct digital frequency synthesizer,read-only-memory (rom)-less,output sinusoidal frequency,spectral purity,wireless network,frequency synthesizer,mathematical analysis,index terms—direct digital frequency synthesizer ddfs,trigonometric quadruple angle formula,41.66 mhz,read-only-memory rom-less,pipeline arithmetic,direct digital frequency synthesizer (ddfs),squarer decomposition,direct digital synthesis,ten-stage pipelining architecture,high-speed read-only-memory less direct digital frequency synthesizer,wireless network.,spurious free dynamic range,read only memory,error correction
Journal
53
Issue
ISSN
Citations 
10
1549-7747
8
PageRank 
References 
Authors
0.66
4
5
Name
Order
Citations
PageRank
Chua-chin Wang1474107.39
Jian-Ming Huang2668.49
Yih-Long Tseng3467.68
Wun-Ji Lin4222.87
Ron Hu55710.76