Name
Abstract | ||
|---|---|---|
The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/FCCM.2007.36 | FCCM |
Keywords | Field | DocType |
data flow analysis,robots,field programmable gate array,detectors,hardware,field programmable gate arrays,fpga,convolution,data flow,embedded computing,embedded system,reconfigurable hardware | Algorithm design,Computer science,Parallel computing,Algorithm,Field-programmable gate array,Software,Modular design,Design space exploration,Reconfigurable computing,Data flow diagram,Hardware architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2940-2 | 8 | 0.87 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Harding Djakou Chati | 1 | 10 | 1.26 |
| Felix Mühlbauer | 2 | 22 | 4.36 |
| Tim Braun | 3 | 10 | 1.26 |
| Christophe Bobda | 4 | 627 | 90.57 |
| Karsten Berns | 5 | 705 | 119.86 |