Name
Abstract | ||
|---|---|---|
For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of configurable permutators. A partially parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multimode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in the efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and hence increase the maximum operating frequency. In addition, shuffled message-passing decoding is adopted, since fewer iterations can be used to achieve the desired bit-error-rate performance. In order to demonstrate the usefulness of the proposed flexible-permutator-based architecture, one single-mode rate-0.84 decoder and two multimode decoders whose code rates range between 0.79 and 0.93 have been implemented. These decoders can achieve multigigabit-per-second throughput. Using the proposed architecture to support lower rate RS-LDPC codes, e.g., rate-0.568 code, is also investigated. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2010.2046964 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
high throughput,code rate,shuffled message-passing decoding,multimode decoder,multimode function,high-rate rs-ldpc codes,partial parallel architecture,single-mode rate decoder,multimode low-density parity-check decoder,configurable permutators,reed-solomon codes,matrix algebra,efficient multimode low-density parity-check,parity-check matrix,low-density parity-check (ldpc) codes,high-rate rs-ldpc code,maximum operating frequency,shuffled iterative decoding,critical-path delay,reed–solomon (rs)-ldpc codes,multimode,high-throughput decoder,multimode shuffled iterative decoder architecture,lower rate rs-ldpc code,high rate,reed-solomon code,structured codes,iterative decoding,flexible-permutator-based architecture,iterative decoder architecture,error statistics,ldpc code,parity check codes,parallel architecture,bit-error-rate performance,multi mode,reed solomon,decoder,bit error rate,single mode,reed solomon code,throughput,low density parity check,message passing,critical path,decoding,parity check matrix | Parity-check matrix,Low-density parity-check code,Matrix (mathematics),Computer science,Parallel computing,Reed–Solomon error correction,Electronic engineering,Soft-decision decoder,Decoding methods,Throughput,Multi-mode optical fiber | Journal |
Volume | Issue | ISSN |
57 | 10 | 1549-8328 |
Citations | PageRank | References |
18 | 0.86 | 32 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yeong-Luh Ueng | 1 | 234 | 34.21 |
| Chung-Jay Yang | 2 | 73 | 5.08 |
| Kuan-Chieh Wang | 3 | 56 | 3.74 |
| Chun-Jung Chen | 4 | 44 | 8.76 |