Paper Info
Title
A deductive technique for diagnosis of bridging faults
Abstract
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behavior. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge and eliminates certain faults. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. The intersection graph implicitly represents all candidate faults, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. The above procedures are performed dynamically and a reduced intersection graph is maintained to reduce memory and simulation time. No dictionary or fault simulation is required. Results are provided for all large ISCAS89 benchmark circuits. For the largest benchmark circuit, the procedure reduces the space of all bridging faults, which is of the order of 10^9 to a few hundred faults on the average in about 30 seconds of execution time.
Year
DOI
Venue
1997
10.1145/266388.266552
ICCAD
Keywords
Field
DocType
path-trace procedure,execution time,iscas89 benchmark circuit,reduced intersection graph,bridging faults,simulation time,diagnosis,certain fault,deductive technique,fault simulation,candidate fault,deduction.,largest benchmark circuit,intersection graph,sequential circuits,combinational circuits
Sequential logic,Logic testing,Computer science,Bridging (networking),Voltage,Intersection graph,Combinational logic,Real-time computing,Execution time,Electronic circuit
Conference
ISBN
Citations 
PageRank 
0-8186-8200-0
45
3.33
References 
Authors
11
2
Name
Order
Citations
PageRank
Srikanth Venkataraman157248.05
W. Kent Fuchs21469279.02