Name
Abstract | ||
|---|---|---|
To suppress the ground bounce noise with a minimal wake-up time penalty, a three-step turn-on strategy and its corresponding power-gating structure are proposed. During the circuit's meta-stable region of operation, specifically, the amount of current flowing through the sleep transistors is precisely controlled while the virtual or circuit power supply is quickly boosted when the internal nodes of the circuit are stable. In 65 nm CMOS technology, simulation results demonstrate that our technique reduces the peak amplitude of the ground bouncing noise by up to 94% as compared to the conventional abrupt turn-on technique. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1840845.1840880 | Low-Power Electronics and Design |
Keywords | Field | DocType |
corresponding power-gating structure,peak amplitude,internal node,conventional abrupt turn-on technique,nm cmos technology,minimal wake-up time penalty,ground bounce noise,meta-stable region,three-step turn-on strategy,circuit power supply,ground bounce,switches,capacitors,noise,system on a chip,transistors | Ground bounce,Capacitor,Computer science,CMOS,Electronic engineering,Power gating,Transistor,Amplitude,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4244-8588-8 | 3 | 0.41 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rahul Singh | 1 | 11 | 1.47 |
| Kim, AhReum | 2 | 9 | 2.56 |
| Soyoung Kim | 3 | 168 | 22.15 |
| Suhwan Kim | 4 | 494 | 74.23 |