Name
Abstract | ||
|---|---|---|
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an important issue because IPs of different sizes may be supported by various vendors. In order to solve routing problems in irregular meshes, modified routing algorithms to detour oversized IPs (OIPs) are needed. However, directly applying fault-tolerant routing algorithms may cause two serious problems: 1) heavy traffic loads around OIPs and 2) unbalanced traffic loads in irregular meshes. In this paper, we propose an OIP avoidance prerouting (OAPR) algorithm to solve the aforementioned problems. The proposed OAPR can make traffic loads evenly spread on the networks and shorten the average paths of packets. Therefore, the networks using the OAPR have lower latency and higher throughput than those using fault- tolerant routing algorithms. In our experiments, four different cases are simulated to demonstrate that the proposed OAPR improves 13.3 percent to 100 percent sustainable throughputs than two previous fault-tolerant routing algorithms. Moreover, the hardware overhead of the OAPR is less than 1 percent compared to the cost of a whole router. Hence, the proposed OAPR algorithm has good performance and is practical for irregular mesh-based OCNs. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TC.2008.60 | IEEE Trans. Computers |
Keywords | Field | DocType |
fault-tolerant routing algorithms,fault-tolerant routing algorithm,proposed oapr algorithm,nanoscale multicore vlsi designs,network routing,irregular mesh-based on-chip networks,heavy traffic,on-chip interconnection networks,previous fault-tolerant,unbalanced traffic,oip avoidance prerouting algorithm,irregular mesh-based onchip networks,modified routing algorithms,fault tolerance,detour oversized ips,and fault-tolerance,reliability,vlsi,traffic-balanced routing algorithm,different case,proposed oapr,irregular mesh-based ocns,irregular mesh,testing,chip,fault tolerant,vlsi design | Polygon mesh,Dynamic Source Routing,Computer science,Static routing,Parallel computing,Destination-Sequenced Distance Vector routing,Fault tolerance,Throughput,Router,Very-large-scale integration,Distributed computing | Journal |
Volume | Issue | ISSN |
57 | 9 | 0018-9340 |
Citations | PageRank | References |
25 | 0.93 | 17 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shu-Yen Lin | 1 | 94 | 13.01 |
| Chun-Hsiang Huang | 2 | 138 | 12.05 |
| Chih-Hao Chao | 3 | 182 | 9.90 |
| Keng-Hsien Huang | 4 | 25 | 1.61 |
| An-Yeu (Andy) Wu | 5 | 97 | 7.92 |