Paper Info
Title
Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures
Abstract
Hardware redundancy is a common method for improving the reliability of a system. The disadvantage of this approach is the hardware overhead and the additional power consumption. This contribution proposes a strategy for implementing low-cost triple modular redundancy (TMR) on coarse-grained reconfigurable architectures (CGRAs). Low-cost TMR is achieved by utilizing unused functional units (FUs) for the redundant computation of results. This is realized by combining the FUs of three processing elements in a fault-tolerant data path. Experimental results show that the proposed approach reduces area in a 8-bit architecture by 12.8% and average power consumption is decreased between 1.6 and 18.6% when compared with a fault-tolerant CGRA implemented by conventional TMR.
Year
DOI
Venue
2011
10.1109/ReConFig.2011.57
Reconfigurable Computing and FPGAs
Keywords
Field
DocType
low-cost triple modular redundancy,average power consumption,hardware overhead,coarse-grained reconfigurable architectures,low-cost tmr,conventional tmr,fault-tolerant data path,additional power consumption,hardware redundancy,fault-tolerant cgra,fault tolerant,redundancy,computer architecture,fault tolerance,functional unit,fault tolerant system,error detection,reliability
Data path,Computer science,Parallel computing,Triple modular redundancy,Real-time computing,Error detection and correction,Fault tolerance,Redundancy (engineering),Computation,Power consumption,Hardware redundancy,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4577-1734-5
11
0.65
References 
Authors
8
5
Name
Order
Citations
PageRank
Thomas Schweizer17410.73
Philipp Schlicker2110.65
Sven Eisenhardt3364.54
Tommy Kuhn4516.75
Wolfgang Rosenstiel51462212.32