Name
Abstract | ||
|---|---|---|
Current interconnect standards propose 16 or even more virtual channels (VCs) for provision of quality of service (QoS). However, VCs increase the complexity of the switch and the scheduling delays. In a previous paper, we have shown how to use only two VCs for full QoS support at the switches. In this paper, we explore thoroughly two alternative switch designs that take advantage of this reduction. We analyze their feasibility in a single chip implementation and show that they get a noticeable performance while greatly reducing the cost and power consumption of the network. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1007/978-3-540-89524-4_35 | ICOIN |
Keywords | DocType | Volume |
alternative switch design,virtual channel,providing full qos,scheduling delay,single chip implementation,noticeable performance,power consumption,previous paper,high-speed switches,full qos support,quality of service,chip | Conference | 5200 |
ISSN | Citations | PageRank |
0302-9743 | 0 | 0.34 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Martínez | 1 | 53 | 6.03 |
| F. J. Alfaro | 2 | 25 | 3.09 |
| J. L. Sánchez | 3 | 4 | 1.42 |
| J. Duato | 4 | 829 | 74.13 |