Paper Info
Title
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme
Abstract
In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting scheme, we explore its data dependency of input and output signals, and thus propose a programmable architecture for different filter banks with low memory usage. For the computation of N×N 2-D DWT with Daubechies 9-7 filter, our architecture requires 9N storage cells and the memory bandwidth requirement is almost one-half of JPEG2000's proposal. This architecture is suitable for VLSI implementation and various real-time image/video applications
Year
DOI
Venue
2001
10.1109/ISCAS.2001.922239
ISCAS (4)
Keywords
Field
DocType
filter bank,line-based programmable architecture,daubechies 9-7 filter,real-time system,memory efficiency,computational complexity,2d discrete wavelet transform,vlsi,filtering theory,programmable circuits,lifting method,discrete wavelet transforms,codecs,computer architecture,wavelet transforms,real time,filtering,wavelet transform,discrete wavelet transform,real time system,memory bandwidth,very large scale integration,lifting scheme,convolution
Memory bandwidth,Lifting scheme,Computer science,Parallel computing,Input/output,Second-generation wavelet transform,Electronic engineering,Discrete wavelet transform,JPEG 2000,Very-large-scale integration,Wavelet transform
Conference
Volume
ISBN
Citations 
4
0-7803-6685-9
15
PageRank 
References 
Authors
1.35
3
4
Name
Order
Citations
PageRank
Wei-Hsin Chang110510.25
Yew-san Lee2649.24
Wen-shiaw Peng3182.44
Chen-Yi Lee41211152.40