Paper Info
Title
Configurable transmitter and systolic channel estimator architectures for data-dependent superimposed training communications systems
Abstract
In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards.
Year
DOI
Venue
2012
10.1155/2012/236372
Int. J. Reconfig. Comp.
Keywords
Field
DocType
ddst channel estimation,monte carlo simulation,verilog hdl,reduced hardware,channel estimator,fpga slice consumption,systolic channel estimator architecture,configurable transmitter,training communications system,64-qam modulation,ddst concept,high performance,data-dependent st
Transmitter,Computer science,Parallel computing,Field-programmable gate array,Mean squared error,Communications system,Communication channel,Modulation,Real-time computing,Verilog,Estimator
Journal
Volume
Citations 
PageRank 
2012,
0
0.34
References 
Authors
8
4
Name
Order
Citations
PageRank
E. Romero-Aguirre131.11
R. Parra-Michel2235.19
Roberto Carrasco-Alvarez3285.80
A. G. Orozco-Lugo4385.16