Name
Abstract | ||
|---|---|---|
The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1023/A:1014968930415 | Journal of Electronic Testing |
Keywords | Field | DocType |
system-on-a-chip,embedded test,BIST | Design for testing,Automatic test pattern generation,Computer science,Automatic test equipment,System testing,Scan chain,Electronic engineering,Real-time computing,White-box testing,Test compression,Built-in self-test,Embedded system | Journal |
Volume | Issue | ISSN |
18 | 2 | 1530-1877 |
ISBN | Citations | PageRank |
0-7695-1016-7 | 27 | 1.47 |
References | Authors | |
19 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rainer Dorsch | 1 | 135 | 12.60 |
| Hans-Joachim Wunderlich | 2 | 1822 | 155.30 |