Paper Info
Title
A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems
Abstract
This paper presents an energy-efficient design and the implementation results of a high speed two transmitter--two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.
Year
DOI
Venue
2012
10.1007/s11265-010-0570-x
Signal Processing Systems
Keywords
Field
DocType
Bit-parallel architecture,MIMO-OFDM,Spatial multiplexing (SM) symbol detector,Wireless LAN
MIMO-OFDM,Computer science,Single antenna interference cancellation,MIMO,Baseband processor,Real-time computing,Spatial multiplexing,Orthogonal frequency-division multiplexing,QR decomposition,Hardware architecture
Journal
Volume
Issue
ISSN
68
1
1939-8018
Citations 
PageRank 
References 
5
0.55
15
Authors
5
Name
Order
Citations
PageRank
Junha Im1101.83
Misuk Cho291.14
Yongmin Jung31711.23
Yunho Jung413624.95
Jaeseok Kim540558.33