Name
Title | ||
|---|---|---|
Steady-State and Dynamic Study of Active Power Filter With Efficient FPGA-Based Control Algorithm |
Abstract | ||
|---|---|---|
A new approach using field-programmable gate array (FPGA) to implement a fully digital control algorithm of active power filter (APF) is proposed in this paper. This FPGA-based controller integrates the whole signal-processing function of an APF, including synchronous-reference-frame transform, low-pass filter, three-phase phase-locked loop, inverter-current controller, etc. By case studies on the principle, performance, and architecture, these control blocks are implemented in real-time and synthesized into a medium-scale FPGA chip by adopting some useful digital-signal-processing techniques, such as pipelining, folding and strength reduction, with respect to minimization of hardware resource and enhancement of operating frequency. As a result, the whole algorithm needs around 5000 logic elements and can run at synchronous system-clock rates of up to 65 MHz. Experimental results on a laboratory prototype are given to demonstrate performance of the proposed approach during steady-state and dynamic operations. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TIE.2008.917151 | IEEE Transactions on Industrial Electronics |
Keywords | Field | DocType |
Steady-state,Active filters,Field programmable gate arrays,Digital control,Low pass filters,Phase locked loops,Control system synthesis,Signal synthesis,Pipeline processing,Hardware | Pipeline (computing),Signal processing,Control theory,Active filter,Control theory,Field-programmable gate array,Control engineering,Electronic engineering,Gate array,Low-pass filter,Engineering,Digital control | Journal |
Volume | Issue | ISSN |
55 | 4 | 0278-0046 |
Citations | PageRank | References |
33 | 4.17 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zeliang Shu | 1 | 56 | 7.71 |
| Yuhua Guo | 2 | 33 | 4.17 |
| Jisan Lian | 3 | 33 | 4.17 |