Name
Title | ||
|---|---|---|
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor |
Abstract | ||
|---|---|---|
The advancement of process technology enables the integration of multiple cores featuring parallel processing. The requirement of extensive memory bandwidth puts a major performance bottleneck in multi-core architectures for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions required by multiple cores, memory access conflicts caused by simultaneous accesses to an identical memory page by two or more cores limit the performance of multi-core architectures. We propose and evaluate the programmable memory address shuffler associated with the novel memory shuffling algorithm integrated in multi-core architectures with parallel memory system. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that access conflicts diminish by analyzing the access pattern of the application. We demonstrate that the shuffling of sub-pages is represented by cyclic linked list which enables partial address shuffling with the minimal number of shuffling table entries. The programmable address shuffler reduces the amount of access conflicts by 83% for pitch-shifting audio decompression. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ASPDAC.2009.4796502 | ASP-DAC |
Keywords | Field | DocType |
identical memory page,pitch-shifting audio decompression,parallel processing,memory transactions,memory access conflict,access conflict,memory addresses,programmable memory address shuffler,multi-core processor,multi-core architecture,novel memory shuffling algorithm,memory access,parallel memory system,multicore processor,extensive memory bandwidth,cyclic linked list,multiprocessing systems,requested memory address,memory transaction,memory page,multicore architectures,multiple cores,partial conflict-relieving programmable address,partial address shuffling,memory bandwidth,programmable address shuffler,parallel memories,memory shuffling algorithm,data mining,indexes,memory management,probability density function,scheduling,system on a chip,gain,multi core processor | Interleaved memory,Computer architecture,Uniform memory access,Physical address,Computer science,Virtual memory,Memory management,Memory address,Memory map,Flat memory model,Embedded system | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-2749-9 | 2 |
PageRank | References | Authors |
0.42 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Su Kwon | 1 | 88 | 17.71 |
| Bontae Koo | 2 | 28 | 5.78 |
| Nak-Woong Eum | 3 | 31 | 9.55 |