Name
Abstract | ||
|---|---|---|
An efficient architecture for a FPGA symmetry FIR filter is proposed that employs M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed RAM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted. Altera APEX20KE is used as a target device. Thus, the proposed architecture has high processing speed and small area. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692725 | 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
Keywords | Field | DocType |
fir filter,field programmable gate arrays,logic,shift registers,finite impulse response filter,ram,fpga,fir filters,multiplier,arithmetic | Partial product,Architecture,Computer science,Field-programmable gate array,Electronic engineering,Multiplier (economics),Multiplication,Distributed arithmetic,Computer hardware,Finite impulse response | Conference |
ISSN | Citations | PageRank |
0271-4302 | 3 | 0.68 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shiann-Shiun Jeng | 1 | 73 | 11.75 |
| Hsing-Chen Lin | 2 | 4 | 1.39 |
| Shu-ming Chang | 3 | 30 | 8.19 |